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MITSUBISHI SEMICONDUCTOR MITSUBISHI SEMICONDUCTOR
PS22054 PS22054
TRANSFER-MOLD TYPE TRANSFER-MOLD TYPE INSULATED TYPE INSULATED TYPE
PS22054
INTEGRATED POWER FUNCTIONS
1200V/15A low-loss 4th generation IGBT inverter bridge for 3 phase DC-to-AC power conversion
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS
* * * * For upper-leg IGBTS :Drive circuit, High voltage high-speed level shifting, Control supply under-voltage (UV) protection. For lower-leg IGBTS : Drive circuit, Control supply under-voltage protection (UV), Short circuit protection (SC). Fault signaling : Corresponding to an SC fault (Lower-side IGBT) or a UV fault (Lower-side supply). Input interface : 5V line CMOS/TTL compatible (High active logic).
APPLICATION AC400V 0.2kW~2.2kW inverter drive for small power motor control.
Fig. 1 PACKAGE OUTLINES
Dimensions in mm
302.54(=76.2) 2.540.3 Heat sink side
12 34 56 78 9 10 11 12 13 14 15 16 17 18 19 20 21
48.60.6
22
23
24
25
26
27
28
18.50.5
2-4.50.2
80.3
10.160.3 670.3 790.5
16.10.3
20.40.5
QR Code
A
42.60.5
Type name , Lot No.
440.5
8.20.5
(2.5) Heat sink side
(2)
Detail : A
All external terminals are treated with lead free solder (ingredient : Sn-Cu) plating.
(0.3)
(1.7)
(2)
(0.3)
1. VUFS 2. VUFB 3. VP1 4. UP 5. VVFS 6. VVFB 7. VP1 8. VP 9. VWFS 10. VWFB 11. VP1 12. VPC 13. WP 14. VN1 15. VNC 16. CIN 17. CFO 18. FO 19. UN 20. VN 21. WN
22. P 23. U 24. V 25. W 26. NU 27. NV 28. NW
27.40.5 340.5
May 2005
MITSUBISHI SEMICONDUCTOR
PS22054
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 2 INTERNAL FUNCTIONS BLOCK DIAGRAM (TYPICAL APPLICATION EXAMPLE)
CBW+ CBW- CBV+ CBV- CBU- CBU+
C1 : Tight tolerance, temp-compensated electrolytic type (Note : The capacitance depends on the PWM control scheme used in the applied system.) C2 : 0.22~2F R-category ceramic capacitor for noise filtering
High-side input (PWM) (5V line) (Note 1,2)
Input signal Input signal Input signal conditioning conditioning conditioning Level shifter Level shifter Level shifter
Protection circuit (UV) Protection circuit (UV) Protection circuit (UV)
C2 C1
(Note 6)
DIP-IPM
Inrush current limiter circuit
P
Drive circuit Drive circuit Drive circuit
AC line input
H-side IGBTS
(Note 4)
U V W
M
AC line output
C Z
(Note 8)
N1 VNC
NU NV NW
L-side IGBTS
CIN
Drive circuit
Z : ZNR (Surge absorber) C : AC filter (Ceramic capacitor 2.2~6.5nF) (Protection against common-mode noise)
Input signal conditioning Fo logic Protection circuit
Control supply Under-Voltage protection (UV)
FO CFO Low-side input (PWM) (5V line) (Note 1, 2) Fault output (5V line) (Note 3, 5)
(Note 7)
VD VNC (15V line)
Note1: 2: 3: 4:
5: 6: 7: 8:
To prevent input signals oscillation, an RC coupling at each input terminal is recommended. By virtue of integrating HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible. Fo output is open drain type. The signal line should be pulled up to the positive side of a 5V supply with an approximate 10k resistor. The wiring between the power DC-link capacitor and the P/N1 terminals should be as short as possible to protect DIP-IPM against catastrophic high surge voltage. For extra precaution, a small film type snubber capacitor (0.1~0.22F, high voltage type) is recommended to mount closely to the P and N1 terminals. Fo output pulse width (tFO) should be determined by connecting external capacitor between CFO and VNC terminals. (Example : tFO=2.4ms(typ.) at CFO=22nF) High voltage (1200V or more) and fast recovery type (less than 100ns) diodes should be used for the bootstrap circuit. It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction. To prevent LVIC from surge destruction, it is recommended to mount a fast recovery type diode between VNC and NU, NV, NW terminals.
Fig. 3 EXTERNAL PART OF THE DIP-IPM PROTECTION CIRCUIT
DIP-IPM
Drive circuit
IC (A)
SC protection trip level
P
H-side IGBTS
U V W
External protection circuit
Shunt resistor (Note 1)
L-side IGBTS
N1
A
NU NV NW 0
Drive circuit
Collector current waveform
C
R B C CIN VNC
Protection circuit
2
tw (s)
(Note 2)
Note1: 2:
In the recommended external protection circuit, please select the RC time constant in the range 1.5~2.0s. To prevent erroneous protection operation, the wiring of A, B, C should be as short as possible.
Short Circuit Protective Function (SC) : SC protection is achieved by sensing the L-side DC-Bus current (through the external shunt resistor) with a suitable filtering time (defined by the RC circuit). When the sensed shunt voltage exceeds the SC trip-level, all the L-side IGBTs are turned OFF and a fault signal (Fo) is output. Since the SC fault may be repetitive, it is recommended to stop the system and check the fault, when the Fo signal is received.
May 2005
MITSUBISHI SEMICONDUCTOR
PS22054
TRANSFER-MOLD TYPE INSULATED TYPE
MAXIMUM RATINGS (Tj = 25C, unless otherwise noted) INVERTER PART
Symbol VCC VCC(surge) VCES IC ICP PC Tj Parameter Supply voltage Supply voltage (surge) Collector-emitter voltage Each IGBT collector current Each IGBT collector current (peak) Collector dissipation Junction temperature Condition Applied between P-NU, NV, NW Applied between P-NU, NV, NW TC = 25C TC = 25C, less than 1ms TC = 25C, per 1 chip (Note 1) Ratings 900 1000 1200 15 30 56.8 -20~+125 Unit V V V A A W C
Note 1 : The maximum junction temperature rating of the power chips integrated within the DIP-IPM is 150C (@ TC 100C) however, to ensure safe operation of the DIP-IPM, the average junction temperature should be limited to Tj(ave) 125C (@ TC 100C).
CONTROL (PROTECTION) PART
Symbol VD VDB VIN VFO IFO VSC Parameter Control supply voltage Control supply voltage Input voltage Fault output supply voltage Fault output current Current sensing input voltage Condition Applied between VP1-VPC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS Applied between UP, VP, WP-VPC, UN, VN, WN-VNC Applied between FO-VNC Sink current at FO terminal Applied between CIN-VNC Ratings 20 20 -0.5~VD+0.5 -0.5~VD+0.5 1 -0.5~VD+0.5 Unit V V V V mA V
TOTAL SYSTEM
Parameter VCC(PROT) Self protection supply voltage limit (short circuit protection capability) Module case operation temperature TC Tstg Storage temperature Viso Isolation voltage Symbol Condition VD = 13.5~16.5V, Inverter part Tj = 125C, non-repetitive, less than 2 s (Note 2) 60Hz, Sinusoidal, AC 1 minute, connection pins to heat-sink plate Ratings 800 -20~+100 -40~+125 2500 Unit V C C Vrms
Note 2 : TC MEASUREMENT POINT
Control terminals
Heat sink boundary Heat-sink
TC
Power terminals
TC
May 2005
MITSUBISHI SEMICONDUCTOR
PS22054
TRANSFER-MOLD TYPE INSULATED TYPE
THERMAL RESISTANCE
Symbol Rth(j-c)Q Rth(j-c)F Rth(c-f) Parameter Junction to case thermal resistance (Note 3) Contact thermal resistance Condition Inverter IGBT part (per 1/6 module) Inverter FWDi part (per 1/6 module) Case to fin, (per 1 module) thermal grease applied Min. -- -- -- Limits Typ. -- -- -- Max. 1.76 2.41 0.047 Unit C/W C/W C/W
Note 3: Grease with good thermal conductivity and long-term endurance should be applied evenly with about +100m~+200m on the contacting surface of DIP-IPM and heat-sink.
ELECTRICAL CHARACTERISTICS (Tj = 25C, unless otherwise noted) INVERTER PART
Symbol VCE(sat) VEC ton trr tc(on) toff tc(off) ICES Parameter Collector-emitter saturation voltage FWDi forward voltage VD = VDB = 15V VIN = 5V, IC = 15A -IC = 15A, VIN = 0V Condition Tj = 25C Tj = 125C Min. -- -- -- 0.8 -- -- -- -- -- -- Limits Typ. 2.7 2.5 2.5 1.5 0.2 0.4 2.8 0.4 -- -- Max. 3.4 3.2 3.0 2.2 -- 0.7 3.8 0.7 1 10 Unit V V s s s s s mA
Switching times
VCC = 600V, VD = VDB = 15V IC = 15A, Tj = 125C, VIN = 0 5V Inductive load (upper-lower arm) Tj = 25C Tj = 125C
Collector-emitter cut-off current
VCE = VCES
CONTROL (PROTECTION) PART
Symbol Parameter Condition Total of VP1-VPC, VN1-VNC VD = VDB = 15V VIN = 5V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS Total of VP1-VPC, VN1-VNC VD = VDB = 15V VIN = 0V VUFB-VUFS, VVFB-VVFS, VWFB-VWFS VSC = 0V, FO circuit pull-up to 5V with 10k VSC = 1V, IFO = 1mA Tj = 25C, VD = 15V (Note 4) VIN = 5V Trip level Reset level Tj 125C Trip level Reset level CFO = 22nF (Note 5) Min. -- -- -- -- 4.9 -- 0.43 0.7 10.0 10.5 10.3 10.8 1.6 2.0 0.8 Limits Typ. -- -- -- -- -- -- 0.48 1.5 -- -- -- -- 2.4 3.0 1.4 Max. 3.70 1.30 3.50 1.30 -- 1.10 0.53 2.0 12.0 12.5 12.5 13.0 -- 4.2 2.0 Unit mA mA mA mA V V V mA V V V V ms V V
ID
Circuit current
VFOH Fault output voltage VFOL VSC(ref) Short circuit trip level Input current IIN UVDBt Supply circuit under-voltage UVDBr protection UVDt UVDr Fault output pulse width tFO ON threshold voltage Vth(on) Applied between UP, VP, WP-VPC, UN, VN, WN-VNC OFF threshold voltage Vth(off) Note 4 : Short circuit protection is functioning only at the low-arms. Please select the value of the external shunt resistor such that the SC triplevel is less than 1.7 times device current rating. 5 : Fault signal is output when the low-arms short circuit or control supply under-voltage protective functions operate. The fault output pulsewidth tFO depends on the capacitance value of CFO according to the following approximate equation : CFO = 9.3 10-6 tFO [F].
May 2005
MITSUBISHI SEMICONDUCTOR
PS22054
TRANSFER-MOLD TYPE INSULATED TYPE
MECHANICAL CHARACTERISTICS AND RATINGS
Parameter Mounting torque Weight Heat-sink flatness Mounting screw : M4 Condition Recommended 1.18 N*m (Note 6) Min. 0.98 -- -50 Limits Typ. -- 77 -- Max. 1.47 -- 100 Unit N*m g m
Note 6: Measurement point of heat-sink flatness
+-
Measurement location
3.25mm
Heat-sink side
- +
Heat-sink side
RECOMMENDED OPERATION CONDITIONS
Symbol VCC VD VDB VD, VDB tdead fPWM IO PWIN(on) 350 VCC 800V, 13.5 VD 16.5V, 13.5 VDB 16.5V, -20C TC 100C, N line wiring inductance less than 10nH (Note 9) Parameter Supply voltage Control supply voltage Control supply voltage Control supply variation Arm shoot-through blocking time PWM input frequency Output r.m.s. current Condition Applied between P-NU, NV, NW Applied between VP1-VPC, VN1-VNC Applied between VUFB-VUFS, VVFB-VVFS, VWFB-VWFS For each input signal, TC 100C TC 100C, Tj 125C VCC = 600V, VD = 15V, fC = 15kHz P.F = 0.8, sinusoidal Tj 125C, TC 100C Min. 350 13.5 13.5 -1 3.3 -- -- (Note 7) (Note 8) Ic 15A 1.5 2.5 Limits Typ. 600 15.0 15.0 -- -- -- -- -- -- Max. 800 16.5 16.5 1 -- 15 5.5 -- -- s 15 < Ic 25.5A 2.7 -- -- -- 5.0 V Unit V V V V/s s kHz Arms
Minimum input pulse width PWIN(off)
VNC VNC variation -5.0 Between VNC-NU, NV, NW (including surge) Note 7 : The output r.m.s. current value depends on the actual application conditions. 8 : DIP-IPM might not make response to the input on signal with pulse width less than PWIN (on). 9 : DIP-IPM might not make response or work properly if the input off signal pulse width is less than PWIN (off).
May 2005
MITSUBISHI SEMICONDUCTOR
PS22054
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 4 THE DIP-IPM INTERNAL CIRCUIT
VUFB VUFS VP1 UP
HVIC1
VCC VB HO VS
DIP-IPM
P IGBT1 Di1
IN COM
U
VVFB VVFS VP1 VP
HVIC2
VCC VB HO VS
IGBT2
Di2
IN COM
V
VWFB VWFS VP1 WP VPC
HVIC3
VCC VB HO VS
IGBT3
Di3
IN COM
W IGBT4 Di4
LVIC
UOUT
VN1
VCC
UVNO
NU IGBT5 Di5
VOUT VVNO
NV IGBT6 Di6
UN VN WN
Fo
UN VN WN Fo GND WVNO CIN WOUT
NW
VNC
CFO
CFO
CIN
May 2005
MITSUBISHI SEMICONDUCTOR
PS22054
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 5 TIMING CHARTS OF THE DIP-IPM PROTECTIVE FUNCTIONS [A] Short-Circuit Protection (Lower-arms only with the external shunt resistor and CR filter)
a1. Normal operation : IGBT ON and carrying current. a2. Short circuit current detection (SC trigger). a3. IGBT gate hard interruption. a4. IGBT turns OFF. a5. FO output with a fixed pulse width determined by the external capacitor CFO. a6. Input = "L " : IGBT OFF a7. Input = "H" : a8. IGBT OFF state in spite of input "H".
Lower-arms control input Protection circuit state SET
a6 a7
RESET
Internal IGBT gate a2 a1 Output current Ic Sense voltage of the shunt resistor SC
a3
a4 a8 SC reference voltage
CR circuit time constant DELAY Error output Fo a5
[B] Under-Voltage Protection (Lower-arm, UVD)
b1. Control supply voltage rising : After the voltage level reaches UVDr, the circuits start to operate when next input is applied. b2. Normal operation : IGBT ON and carrying current. b3. Under voltage trip (UVDt). b4. IGBT OFF in spite of control input condition. b5. FO keeps output during the UV period, however, FO pulse is not less than the fixed width for very short UV interval. b6. Under voltage reset (UVDr). b7. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state UVDr
RESET
SET
RESET b6
Control supply voltage VD
b1
UVDt
b3 b4
b2 Output current Ic
b7
Error output Fo
b5
May 2005
MITSUBISHI SEMICONDUCTOR
PS22054
TRANSFER-MOLD TYPE INSULATED TYPE
[C] Under-Voltage Protection (Upper-side, UVDB)
c1. Control supply voltage rises : After the voltage reaches UVDBr, the circuits start to operate when next input is applied. c2. Normal operation : IGBT ON and carrying current. c3. Under voltage trip (UVDBt). c4. IGBT OFF in spite of control input signal level, but there is no FO signal output. c5. Under voltage reset (UVDBr). c6. Normal operation : IGBT ON and carrying current.
Control input
Protection circuit state UVDBr Control supply voltage VDB
RESET
SET
RESET
c1
UVDBt
c5 c3 c4 c6
c2 Output current Ic High-level (no fault output)
Error output Fo
Fig. 6 MCU I/O INTERFACE CIRCUIT
5V line
10k
DIP-IPM
UP,VP,WP,UN,VN,WN
MCU
Fo VNC(Logic)
Note : RC coupling at each input (parts shown dotted) may change depending on the PWM control scheme used in the application and the wiring impedance of the application's printed circuit board. The DIP-IPM input signal section integrates a 2.5k(min) pull-down resistor. Therefore, when using a external filtering resistor, pay attention to the turn-on threshold voltage requirement.
Fig. 7 WIRING CONNECTION WITH 1 SHUNT RESISTOR
Using low inductance chip resistor and reducing wiring length to minimize the wiring inductance.
DIP-IPM
NU NV VNC NW
Shunt resistor Please make the wiring connection of shunt resistor to GND as short as possible.
Please insert fast recovery type diode between VNC and NU, NV, NW terminals.
For 3 shunt resistors connection, please refer to Fig.9.
May 2005
MITSUBISHI SEMICONDUCTOR
PS22054
TRANSFER-MOLD TYPE INSULATED TYPE
Fig. 8 AN EXAMPLE OF TYPICAL DIP-IPM APPLICATION CIRCUT WITH 1 SHUNT RESISTOR
C1:Tight tolerance temp-compensated electrolytic type C2,C3: 0.1~0.22F R-category ceramic capacitor for noise filtering. (Note: The capacitance value depends on the PWM control used in the applied system.)
C2 C1
VUFB VUFS VP1 HVIC1
VCC VB HO VS
DIP-IPM
P
C3
UP
IN COM
U
C2 C1
VVFB VVFS VP1 HVIC2
VCC IN COM VB HO VS
C3
VP
V
C2 C1
VWFB VWFS VP1 HVIC3
VCC IN COM VB HO VS
M
C3
WP VPC
MCU
W
LVIC
UOUT
VN1
VCC
C3 5V line
UVNO
NU
VOUT VVNO
NV
UN VN WN Fo VNC
UN VN WN Fo CIN GND CFO WOUT WVNO
NW
If this wiring is too long, short circuit might be caused.
C CFO C4(CFO) CIN R1 C5 A B
Shunt resistor N1
15V line
The long wiring of GND might generate noise on input and cause IGBT to be malfunction.
If this wiring is too long, the SC level fluctuation might be larger and cause SC malfunction.
Note 1 : 2: 3: 4: 5: 6: 7: 8: 9: 10: 11:
To avoid malfunction, the wiring of each input should be as short as possible. (less than 2-3cm) By virtue of integrating HVIC inside the module, direct coupling to MCU terminals without any opto-coupler or transformer isolation is possible. Fo output is open drain type. The signal line should be pulled up to the positive side of a 5V supply with an approximate 10k resistor. Fo output pulse width (tFO) should be determined by connecting external capacitor C4 between CFO and VNC terminals. (Example : tFO=2.4ms(typ.) at CFO=22nF) Input signal is High-Active type. There is a 2.5k (Min.) resistor inside IC to pull down each input signal line to GND. When employing RC coupling circuits at each input, set up RC couple such that input signal agree with turn-off/turn-on threshold voltage. To prevent errors of the protection function, the wiring of A, B, C should be as short as possible. The time constant R5C1 of the protection circuit should be selected in the range of 1.5~2s. SC interrupting time might vary with the wiring pattern. All capacitors should be mounted as close to the terminals of the DIP-IPM as possible. To prevent surge destruction, the wiring between the smoothing capacitor and the P&N1 terminals should be as short as possible. Generally a 0.1~0.22F snubber between the P&N1 terminals is recommended. It is recommended to insert a Zener diode (24V/1W) between each pair of control supply terminals to prevent surge destruction. To prevent LVIC from surge destruction, it is recommended to mount a fast recovery type diode between VNC and NU, NV, NW terminals.
DIP-IPM
Drive circuit P
Fig. 9 EXAMPLE OF EXTERNAL PROTECTION CIRCUIT WITH 3 SHUNT RESISTORS
The time constant RC of external comparator should be selected in the range of 1.5~2s. SC interrupting time might vary with the wiring pattern. The threshold voltage Vref should be set up the same rating of short circuit trip level (VSC(ref) typ. 0.48V). * Please select the external shunt resistance such that the SC trip-level is less than 1.7 times of the current rating. * To avoid malfunction, the wiring of each input should be as short as possible. * OR circuit output level should be set up the rating of short circuit trip level (VSC(ref) typ. 0.48V). * For extra precaution, please refer to Fig.8
* *
H-side IGBTS U V W L-side IGBTS
External protection circuit
R NW NV NU C Vref R C Vref R Shunt resistor C Vref
+ - + - + -
Comparator OR logic circuit
Drive circuit Protection circuit CIN
VNC
May 2005

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